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CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committee

Scope

Today, we are in the internet-of-things (IoT) era – an era of sensors and components connected across a high speed communication infrastructure with analysis by massive data center “clouds”. The building blocks are systems-on-chip (SoC) integrated with several diverse IP modules. Analog and mixed-signal (AMS) circuits form many of the critical components of SoCs that push the boundaries of high bandwidth and low power. AMS circuits, such as phase-locked loops, sensors, amplifiers, wired and wireless interfaces are often embedded in a chip with limited controllability to access them.

The demand for high performance, high bandwidth and low power has resulted in AMS designs operating at their margins. The unimaginable levels of integration has come at the cost of increased manufacturing process variations, vulnerability to defects, and accelerated device aging. In this scenario, verifying and validating AMS circuits, which are particularly sensitive to variations and electrical noise, in both pre-silicon and post-silicon phases, has become a great challenge. Effective diagnosis to improve AMS yield, and manufacturing test methods to detect catastrophic faults and unexpected process excursions that have contributed to increased AMS-related customer returns are a necessity. Further, sensitive AMS circuits such as those used in health and automotive products need to have a high degree of in-field reliability requiring fault tolerance and adaptive operation. Since most AMS circuits are often the gateways to a SoC, ensuring their secure design is of vital im portance to prevent compromising the security of the chip. These quality objectives should be met under market requirements of aggressively low product cost and product cycle time.

The IEEE Workshop on Test and Validation of High Speed Analog Circuits (TVHSAC) is a forum to address the pre-silicon and post-silicon validation, manufacturing test, in-field reliability and security challenges in AMS circuits and systems.

The areas of interest include (but not limited to):

Built-in test and design-for-test
Self-healing, self-calibration and self-adaptation techniques
Sample selection for pre-silicon and post-silicon validation
Behavioral modeling
Efficient mixed-signal simulation
Analog fault modeling and fault simulation
Analog and mixed-signal diagnosis
Reliable and secure AMS circuit design
Test access mechanism
Analog test bus design
SERDES test and characterization
RF circuits test and characterization
High speed data converter test and
characterization
High speed PLL test and characterization
Precision delay-line test and
characterization
Clock jitter and skew measurement
Phase noise measurement
AC and DC supply noise measurement
ATE technology
Board technology
Economics of test and yield optimization

Submissions

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Prospective authors are invited to submit scientific papers and/or posters. Paper submissions consist of either extended summaries or full papers, in PDF following IEEE two-column conference proceedings format. Full papers should not exceed six printed pages. Poster submissions consist of extended summaries. Proposals for special sessions, hot topics, and panel sessions are also invited.

Key Dates

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Paper submissions are due by July 31, 2015, while poster submissions are due by August 15, 2015. Authors will be notified by August 28, 2015. Final manuscripts of accepted papers, posters, special sessions, hot topics and panel sessions are due by September 15, 2015, to be included in the workshop digest upon authors’ choice. For details on submissions please visit http://tima.imag.fr/conferences/tvhsac.

Additional Information

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For information contact:

Suriya Natarajan - suriyaprakash.natarajan@intel.com

Manuel Barragan - manuel.barragan@imag.fr

Committee

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General Chair

Suriya Natarajan, Intel

Vice General Chair

Yervant Zorian, Synopsys

Finance Chair

Chen-Huan Chiang, Alcatel-Lucent

Publicity Chairs

Yiorgos Makris, UT Dallas Ke Huang, SDSU

Program Chair

Manuel J. Barragan, TIMA

Program Committee

Jacob Abraham, UT Austin
Ahcène Bouncer, U. Brest
Kenneth Butler, TI
Abhijit Chatterjee, Georgia Tech
Jerzy Dabrowsky, Linkoping U.
Emeric De Foucauld, CEA-LETI
Ke Huang, SDSU
Jaeha Kim, Seoul National U.
Gildas Léger, IMSE-CNM
Xin Li, CMU
Amit Majumdar, Xilinx
Yiorgos Makris, UT Dallas
Srinivas Modekurty, Intel
Sule Ozev, ASU
Arijit Raychowdhury, Georgia Tech
Gordon Roberts, McGill U.
Saghir Shaikh, Broadcom
C.-J. Richard Shi, U. Washington
Mustapha Slamani, IBM
Mani Soma, U. Washington
Haralampos Stratigopoulos, LIP6
Stephen Sunter, Mentor Graphics
Shoba Vasudevan, U. Illinois UC
Amir Zjajo, TU Delft

For more information, visit us on the web at: http://tima.imag.fr/conferences/tvhsac

The 4th IEEE International Workshop on Test and Validation of High Speed Analog Circuits is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).